Estabilidad económico-financiera y derecho internacional

Trabajo realizado en el marco del Proyecto de Investigación DER2010-21083El presente estudio analiza las respuestas que desde el Derecho Internacional Público se han articulado para hacer frente a la crisis económica y financiera global que se desencadenó en 2008 y cómo la estabilidad financiera se ha convertido en un bien público global necesitado de protección. Las normas monetarias y financieras internacionales están modificándose sustancialmente para garantizar la estabilidad económica y financiera en la economía globalizada actual como consecuencia de esta grave crisis. Esta reforma del derecho monetario y financiero internacional ha sido impulsada a nivel político por el G-20, que se ha convertido en el epicentro de la gobernanza económica y financiera internacional. A nivel técnico-económico el FMI ha sido la organización más activa y la crisis ha impactado sobre su organización y funcionamiento a la vez que ha reforzado su poder como consecuencia del aumento de sus préstamos a países con dificultades, incluso de la UE. A nivel técnico-financiero, la respuesta ha sido liderada por el nuevo Consejo de Estabilidad Financiera, vinculado con el Banco de Pagos Internacionales, al que se le ha encomendado la ingente labor de coordinar la producción de soft law internacional en materia financiera, realizada por numerosos comités intergubernamentales

Reliability-aware circuit design to mitigate impact of device defects and variability in emerging memristor-based applications

In the last decades, semiconductor industry has fostered a fast downscale in technology, propelling the large scale integration of CMOS-based systems. The benefits in miniaturization are numerous, highlighting faster switching frequency, lower voltage supply and higher device density. However, this aggressive scaling trend it has not been without challenges, such as leakage currents, yield reduction or the increase in the overall system power dissipation. New materials, changes in the device structures and new architectures are key to keep the miniaturization trend. It is foreseen that 2D integration will eventually come to an insurmountable physical and economic limit, in which new strategic directions are required, such as the development of new device structures, 3D architectures or heterogeneous systems that takes advantage of the best of different technologies, both the ones already consolidated as well as emergent ones that provide performance and efficiency improvements in applications. In this context, memristor arises as one of several candidates in the race to find suitable emergent devices. Memristor, a blend of the words memory and resistor, is a passive device postulated by Leon Chua in 1971. In contrast with the other fundamental passive elements, memristors have the distinctive feature of modifying their resistance according to the charge that passes through these devices, and remaining unaltered when charge no longer flows. Although when it appeared no physical device implementation was acknowledged, HP Labs claimed in 2008 the manufacture of the first real memristor. This milestone triggered an unexpectedly high research activity about memristors, both in searching new materials and structures as well as in potential applications. Nowadays, memristors are not only appreciated in memory systems by their nonvolatile storage properties, but in many other fields, such as digital computing, signal processing circuits, or non-conventional applications like neuromorphic computing or chaotic circuits. In spite of their promising features, memristors show a primarily downside: they show significant device variation and limited lifetime due degradation compared with other alternatives. This Thesis explores the challenges that memristor variation and malfunction imposes in potential applications. The main goal is to propose circuits and strategies that either avoid reliability problems or take advantage of them. Throughout a collection of scenarios in which reliability issues are present, their impact is studied by means of simulations. This thesis is contextualized and their objectives are exposed in Chapter 1. In Chapter 2 the memristor is introduced, at both conceptual and experimental levels, and different compact levels are presented to be later used in simulations. Chapter 3 deepens in the phenomena that causes the lack of reliability in memristors, and models that include these defects in simulations are provided. The rest of the Thesis covers different applications. Therefore, Chapter 4 exhibits nonvolatile memory systems, and specifically an online test method for faulty cells. Digital computing is presented in Chapter 5, where a solution for the yield reduction in logic operations due to memristors variability is proposed. Lastly, Chapter 6 reviews applications in the analog domain, and it focuses in the exploitation of results observed in faulty memristor-based interconnect mediums for chaotic systems synchronization purposes. Finally, the Thesis concludes in Chapter 7 along with perspectives about future work.Este trabajo desarrolla un novedoso dispositivo condensador basado en el uso de la nanotecnología. El dispositivo parte del concepto existente de metal-aislador-metal (MIM), pero en lugar de una capa aislante continua, se utilizan nanopartículas dieléctricas. Las nanopartículas son principalmente de óxido de silicio (sílice) y poliestireno (PS) y los valores de diámetro son 255nm y 295nm respectivamente. Las nanopartículas contribuyen a una alta relación superficie/volumen y están fácilmente disponibles a bajo costo. La tecnología de depósito desarrollada en este trabajo se basa en la técnica de electrospray, que es una tecnología de fabricación ascendente (bottom-up) que permite el procesamiento por lotes y logra un buen compromiso entre una gran superficie y un bajo tiempo de depósito. Con el objetivo de aumentar la superficie de depósito, la configuración de electrospray ha sido ajustada para permitir áreas de depósito de 1cm2 a 25cm2. El dispositivo fabricado, los llamados condensadores de metal aislante de nanopartículas (NP-MIM) ofrecen valores de capacidad más altos que un condensador convencional similar con una capa aislante continua. En el caso de los NP-MIM de sílice, se alcanza un factor de hasta 1000 de mejora de la capacidad, mientras que los NP-MIM de poliestireno exhibe una ganancia de capacidad en el rango de 11. Además, los NP-MIM de sílice muestran comportamientos capacitivos en específicos rangos de frecuencias que depende de la humedad y el grosor de la capa de nanopartículas, mientras que los NP-MIM de poliestireno siempre mantienen su comportamiento capacitivo. Los dispositivos fabricados se han caracterizado mediante medidas de microscopía electrónica de barrido (SEM) complementadas con perforaciones de haz de iones focalizados (FIB) para caracterizar la topografía de los NP-MIMs. Los dispositivos también se han caracterizado por medidas de espectroscopia de impedancia, a diferentes temperaturas y humedades. El origen de la capacitancia aumentada está asociado en parte a la humedad en las interfaces de las nanopartículas. Se ha desarrollado un modelo de un circuito basado en elementos distribuidos para ajustar y predecir el comportamiento eléctrico de los NP-MIMs. En resumen, esta tesis muestra el diseño, fabricación, caracterización y modelización de un nuevo y prometedor condensador nanopartículas metal-aislante-metal que puede abrir el camino al desarrollo de una nueva tecnología de supercondensadores MIM.Postprint (published version

Reliability-aware circuit design to mitigate impact of device defects and variability in emerging memristor-based applications

In the last decades, semiconductor industry has fostered a fast downscale in technology, propelling the large scale integration of CMOS-based systems. The benefits in miniaturization are numerous, highlighting faster switching frequency, lower voltage supply and higher device density. However, this aggressive scaling trend it has not been without challenges, such as leakage currents, yield reduction or the increase in the overall system power dissipation. New materials, changes in the device structures and new architectures are key to keep the miniaturization trend. It is foreseen that 2D integration will eventually come to an insurmountable physical and economic limit, in which new strategic directions are required, such as the development of new device structures, 3D architectures or heterogeneous systems that takes advantage of the best of different technologies, both the ones already consolidated as well as emergent ones that provide performance and efficiency improvements in applications. In this context, memristor arises as one of several candidates in the race to find suitable emergent devices. Memristor, a blend of the words memory and resistor, is a passive device postulated by Leon Chua in 1971. In contrast with the other fundamental passive elements, memristors have the distinctive feature of modifying their resistance according to the charge that passes through these devices, and remaining unaltered when charge no longer flows. Although when it appeared no physical device implementation was acknowledged, HP Labs claimed in 2008 the manufacture of the first real memristor. This milestone triggered an unexpectedly high research activity about memristors, both in searching new materials and structures as well as in potential applications. Nowadays, memristors are not only appreciated in memory systems by their nonvolatile storage properties, but in many other fields, such as digital computing, signal processing circuits, or non-conventional applications like neuromorphic computing or chaotic circuits. In spite of their promising features, memristors show a primarily downside: they show significant device variation and limited lifetime due degradation compared with other alternatives. This Thesis explores the challenges that memristor variation and malfunction imposes in potential applications. The main goal is to propose circuits and strategies that either avoid reliability problems or take advantage of them. Throughout a collection of scenarios in which reliability issues are present, their impact is studied by means of simulations. This thesis is contextualized and their objectives are exposed in Chapter 1. In Chapter 2 the memristor is introduced, at both conceptual and experimental levels, and different compact levels are presented to be later used in simulations. Chapter 3 deepens in the phenomena that causes the lack of reliability in memristors, and models that include these defects in simulations are provided. The rest of the Thesis covers different applications. Therefore, Chapter 4 exhibits nonvolatile memory systems, and specifically an online test method for faulty cells. Digital computing is presented in Chapter 5, where a solution for the yield reduction in logic operations due to memristors variability is proposed. Lastly, Chapter 6 reviews applications in the analog domain, and it focuses in the exploitation of results observed in faulty memristor-based interconnect mediums for chaotic systems synchronization purposes. Finally, the Thesis concludes in Chapter 7 along with perspectives about future work.Este trabajo desarrolla un novedoso dispositivo condensador basado en el uso de la nanotecnología. El dispositivo parte del concepto existente de metal-aislador-metal (MIM), pero en lugar de una capa aislante continua, se utilizan nanopartículas dieléctricas. Las nanopartículas son principalmente de óxido de silicio (sílice) y poliestireno (PS) y los valores de diámetro son 255nm y 295nm respectivamente. Las nanopartículas contribuyen a una alta relación superficie/volumen y están fácilmente disponibles a bajo costo. La tecnología de depósito desarrollada en este trabajo se basa en la técnica de electrospray, que es una tecnología de fabricación ascendente (bottom-up) que permite el procesamiento por lotes y logra un buen compromiso entre una gran superficie y un bajo tiempo de depósito. Con el objetivo de aumentar la superficie de depósito, la configuración de electrospray ha sido ajustada para permitir áreas de depósito de 1cm2 a 25cm2. El dispositivo fabricado, los llamados condensadores de metal aislante de nanopartículas (NP-MIM) ofrecen valores de capacidad más altos que un condensador convencional similar con una capa aislante continua. En el caso de los NP-MIM de sílice, se alcanza un factor de hasta 1000 de mejora de la capacidad, mientras que los NP-MIM de poliestireno exhibe una ganancia de capacidad en el rango de 11. Además, los NP-MIM de sílice muestran comportamientos capacitivos en específicos rangos de frecuencias que depende de la humedad y el grosor de la capa de nanopartículas, mientras que los NP-MIM de poliestireno siempre mantienen su comportamiento capacitivo. Los dispositivos fabricados se han caracterizado mediante medidas de microscopía electrónica de barrido (SEM) complementadas con perforaciones de haz de iones focalizados (FIB) para caracterizar la topografía de los NP-MIMs. Los dispositivos también se han caracterizado por medidas de espectroscopia de impedancia, a diferentes temperaturas y humedades. El origen de la capacitancia aumentada está asociado en parte a la humedad en las interfaces de las nanopartículas. Se ha desarrollado un modelo de un circuito basado en elementos distribuidos para ajustar y predecir el comportamiento eléctrico de los NP-MIMs. En resumen, esta tesis muestra el diseño, fabricación, caracterización y modelización de un nuevo y prometedor condensador nanopartículas metal-aislante-metal que puede abrir el camino al desarrollo de una nueva tecnología de supercondensadores MIM

Reliability-aware circuit design to mitigate impact of device defects and variability in emerging memristor-based applications

In the last decades, semiconductor industry has fostered a fast downscale in technology, propelling the large scale integration of CMOS-based systems. The benefits in miniaturization are numerous, highlighting faster switching frequency, lower voltage supply and higher device density. However, this aggressive scaling trend it has not been without challenges, such as leakage currents, yield reduction or the increase in the overall system power dissipation. New materials, changes in the device structures and new architectures are key to keep the miniaturization trend. It is foreseen that 2D integration will eventually come to an insurmountable physical and economic limit, in which new strategic directions are required, such as the development of new device structures, 3D architectures or heterogeneous systems that takes advantage of the best of different technologies, both the ones already consolidated as well as emergent ones that provide performance and efficiency improvements in applications. In this context, memristor arises as one of several candidates in the race to find suitable emergent devices. Memristor, a blend of the words memory and resistor, is a passive device postulated by Leon Chua in 1971. In contrast with the other fundamental passive elements, memristors have the distinctive feature of modifying their resistance according to the charge that passes through these devices, and remaining unaltered when charge no longer flows. Although when it appeared no physical device implementation was acknowledged, HP Labs claimed in 2008 the manufacture of the first real memristor. This milestone triggered an unexpectedly high research activity about memristors, both in searching new materials and structures as well as in potential applications. Nowadays, memristors are not only appreciated in memory systems by their nonvolatile storage properties, but in many other fields, such as digital computing, signal processing circuits, or non-conventional applications like neuromorphic computing or chaotic circuits. In spite of their promising features, memristors show a primarily downside: they show significant device variation and limited lifetime due degradation compared with other alternatives. This Thesis explores the challenges that memristor variation and malfunction imposes in potential applications. The main goal is to propose circuits and strategies that either avoid reliability problems or take advantage of them. Throughout a collection of scenarios in which reliability issues are present, their impact is studied by means of simulations. This thesis is contextualized and their objectives are exposed in Chapter 1. In Chapter 2 the memristor is introduced, at both conceptual and experimental levels, and different compact levels are presented to be later used in simulations. Chapter 3 deepens in the phenomena that causes the lack of reliability in memristors, and models that include these defects in simulations are provided. The rest of the Thesis covers different applications. Therefore, Chapter 4 exhibits nonvolatile memory systems, and specifically an online test method for faulty cells. Digital computing is presented in Chapter 5, where a solution for the yield reduction in logic operations due to memristors variability is proposed. Lastly, Chapter 6 reviews applications in the analog domain, and it focuses in the exploitation of results observed in faulty memristor-based interconnect mediums for chaotic systems synchronization purposes. Finally, the Thesis concludes in Chapter 7 along with perspectives about future work.Este trabajo desarrolla un novedoso dispositivo condensador basado en el uso de la nanotecnología. El dispositivo parte del concepto existente de metal-aislador-metal (MIM), pero en lugar de una capa aislante continua, se utilizan nanopartículas dieléctricas. Las nanopartículas son principalmente de óxido de silicio (sílice) y poliestireno (PS) y los valores de diámetro son 255nm y 295nm respectivamente. Las nanopartículas contribuyen a una alta relación superficie/volumen y están fácilmente disponibles a bajo costo. La tecnología de depósito desarrollada en este trabajo se basa en la técnica de electrospray, que es una tecnología de fabricación ascendente (bottom-up) que permite el procesamiento por lotes y logra un buen compromiso entre una gran superficie y un bajo tiempo de depósito. Con el objetivo de aumentar la superficie de depósito, la configuración de electrospray ha sido ajustada para permitir áreas de depósito de 1cm2 a 25cm2. El dispositivo fabricado, los llamados condensadores de metal aislante de nanopartículas (NP-MIM) ofrecen valores de capacidad más altos que un condensador convencional similar con una capa aislante continua. En el caso de los NP-MIM de sílice, se alcanza un factor de hasta 1000 de mejora de la capacidad, mientras que los NP-MIM de poliestireno exhibe una ganancia de capacidad en el rango de 11. Además, los NP-MIM de sílice muestran comportamientos capacitivos en específicos rangos de frecuencias que depende de la humedad y el grosor de la capa de nanopartículas, mientras que los NP-MIM de poliestireno siempre mantienen su comportamiento capacitivo. Los dispositivos fabricados se han caracterizado mediante medidas de microscopía electrónica de barrido (SEM) complementadas con perforaciones de haz de iones focalizados (FIB) para caracterizar la topografía de los NP-MIMs. Los dispositivos también se han caracterizado por medidas de espectroscopia de impedancia, a diferentes temperaturas y humedades. El origen de la capacitancia aumentada está asociado en parte a la humedad en las interfaces de las nanopartículas. Se ha desarrollado un modelo de un circuito basado en elementos distribuidos para ajustar y predecir el comportamiento eléctrico de los NP-MIMs. En resumen, esta tesis muestra el diseño, fabricación, caracterización y modelización de un nuevo y prometedor condensador nanopartículas metal-aislante-metal que puede abrir el camino al desarrollo de una nueva tecnología de supercondensadores MIM

Comunicació digital a través d’un únic pla conductor

En aquest projecte es realitza un estudi de l’autonomia de l’alimentació d’un sistema de comunicació entre dispositius electrònics a través d’un medi bidimensional. Aquest sistema conté diferents dispositius que intercanvien informació per mitjà d’un pla conductor (una taula, una paret...). Dos tipus de dispositius són utilitzats: un mestre i un o més esclaus. El mestre controla tot el procés de comunicació i els esclaus resten esperant ordres del mestre i li envien informació. Un microcontrolador controla cada dispositiu. Addicionalment, es mostra una aplicació pràctica del sistema i es crea una aplicació informàtica per tal de monitorar tota l’activitat. En primer lloc, es revisa l’estat de l’art sobre el tema associat al projecte i es dóna una visió global del principi de funcionament del sistema, tant a nivell de hardware com a nivell de software. En el cos central del document es troba el procediment que s’ha utilitzat per a la consecució del projecte i les justificacions necessàries. Finalment, es mostren els resultats obtinguts, les possibles millores que es podrien realitzar i es valora l’efectivitat del sistema aconseguit, en comparació a d’altres que existeixen en l’actualitat. Els annexos contenen altres aspectes d’interès del projecte, com el cost econòmic, el impacte ambiental, els esquemàtics dels dispositius i tot el codi implementat

Protección de los principios del Estado de Derecho en la Unión Europea mediante la condicionalidad financiera

The rule of law is one of the fundamental values ​​of the European Union. The proliferation of “illiberal” governments has multiplied the violations of this value and the limitations of the EU's right to protect it have been revealed. For this reason, an additional procedure has been created to safeguard the rule of law value, which uses the mechanism of financial conditionality, through Regulation 2020/2092. Poland and Hungary have attacked this Regulation with their respective appeals for annulment and the CJEU has confirmed its compatibility with primary law, clearing the way for its application by the Commission and the Council.El Estado de derecho es uno de los valores fundamentales de la Unión Europea. La proliferación de gobiernos “iliberales” ha multiplicado las violaciones de este valor y se han puesto de manifiesto las limitaciones del derecho de la UE para protegerlo. Por ello, se ha creado un procedimiento adicional para salvaguardar el valor Estado de Derecho, que utiliza el mecanismo de la condicionalidad financiera, mediante el Reglamento 2020/2092. Polonia y Hungría han atacado dicho Reglamento con sendos recursos de anulación y el TJUE ha confirmado su compatibilidad con el derecho originario, despejando el camino para su aplicación por la Comisión y el Consejo

Alternative memristor-based interconnect topologies for fast adaptive synchronization of chaotic circuits

© 2020 Elsevier. This manuscript version is made available under the CC-BY-NC-ND 4.0 license http://creativecommons.org/licenses/by-nc-nd/4.0/Resistive switching devices (memristors) constitute an emerging device technology promising for a vari- ety of applications that are currently being studied. In this context, the use of memristors as coupling el- ements of the dynamics of chaotic circuits for adaptive synchronization purposes, was recently proposed and the passive crossbar array was evaluated as target interconnect medium. Nonetheless, memristors may suffer from defects and degradation. Therefore, this work evaluates the impact of memristor switch- ing faults in an adaptive chaotic synchronization scheme, exploring at the same time the fault-tolerance of the crossbar architecture. Moreover, inspired from our observations in the stuck-at-OFF fault analy- sis of the memristive crossbar, some alternative scalable memristive interconnect patterns are suggested, whose performance is found independent of the number of interconnected chaotic circuits, requiring a much smaller number of total memristors than the crossbar array. All simulations are based on an ac- curate physics-based model of a bipolar memristor with filamentary switching mechanism. Based on our results, using the alternative topologies instead of the crossbar array leads to significant savings in the synchronization time that increase with the number of interconnected chaotic units, at the cost of more limited scaling capability and fault-tolerance.This work was supported in part by the Chilean research Grants ANID REDES ETAPA INICIAL 2017 No. REDI170604, ANID FONDECYT INICIACION 11180706, ANID BASAL FB0008, and by the Spanish MINECO and ERDF under Grant TEC2016-75151-C3-2-R.Peer ReviewedPostprint (author's final draft

Experience on material implication computing with an electromechanical memristor emulator

Memristors are being considered as a promising emerging device able to introduce new paradigms in both data storage and computing. In this paper the authors introduce the concept of a quasi-ideal experimental device that emulates the fundamental behavior of a memristor based on an electro- mechanical organization. By using this emulator, results about the experimental implementation of an unconventional material implication-based data-path equivalent to the i-4004 are presented and experimentally demonstrated. The use of the proposed quasi-ideal device allows the evaluation of this new computing paradigm, based on the resistance domain, without incorporating the disturbance of process and cycle to cycle variabilities observed in real nowadays devices that cause a limit in yield and behavior.Peer ReviewedPostprint (published version

Language as construction of thinking and practices in educational exclusion

Esta comunicación versa sobre medidas para atender a la diversidad y revertir el desenganche y el riesgo de abandono en la etapa de Educación Secundaria Obligatoria (ESO) en la Comunidad de Murcia (CARM), llevando a cabo un análisis interpretativo y crítico del discurso de la normativa oficial sobre el tema. Se plantean ciertos referentes teóricos sobre el etiquetaje tipificación, calificaciones y clasificación del alumnado y las implicaciones que comportan, y se clarifica el proceso seguido en el análisis de contenido del discurso, la generación y aplicación de las categorías aplicadas. Los resultados alcanzados revelan la diferenciación extrema de los procesos de tipificación, la enorme fragmentación de las medidas dispuestas y los criterios establecidos para derivar hacia ellas al alumnado, los aspectos normativamente regulados y las lagunas u omisiones. Las conclusiones alertan de los riesgos de segregación que tales decisiones representan y abogan por acciones más integrales y una mayor implicación por los centros en su conjuntoThis communication centers on the measures to deal with diversity and revert the disengagement and risk of early school leaving in the Educación Secundaria Obligatoria (Compulsory Secondary-School Education) in the Community of Murcia (CARM), carrying out an interpretative and critical analysis of the text with the Governmental regulations about the topic. Some theoretical references about the labeling, categorization, grading and classification of the students are considered as well as the implied consequences, and the process followed in the analysis of the content of the speech, the generation and application of the applied categories is clarified. The results achieved show an extreme differentiation of the processes of categorization, the enormous fragmentation of the mandated measures and the established criteria to reroute the students to them, the aspects regulated by norms and lapses or omissions. The conclusions warn about the risks of segregation that such decisions represent and stand for more integral actions and greater implications for schools as a whol

An Approach to Distance Estimation with Stereo Vision Using Address-Event-Representation

Image processing in digital computer systems usually considers the visual information as a sequence of frames. These frames are from cameras that capture reality for a short period of time. They are renewed and transmitted at a rate of 25-30 fps (typical real-time scenario). Digital video processing has to process each frame in order to obtain a result or detect a feature. In stereo vision, existing algorithms used for distance estimation use frames from two digital cameras and process them pixel by pixel to obtain similarities and differences from both frames; after that, depending on the scene and the features extracted, an estimate of the distance of the different objects of the scene is calculated. Spike-based processing is a relatively new approach that implements the processing by manipulating spikes one by one at the time they are transmitted, like a human brain. The mammal nervous system is able to solve much more complex problems, such as visual recognition by manipulating neuron spikes. The spike-based philosophy for visual information processing based on the neuro-inspired Address-Event-Representation (AER) is achieving nowadays very high performances. In this work we propose a two- DVS-retina system, composed of other elements in a chain, which allow us to obtain a distance estimation of the moving objects in a close environment. We will analyze each element of this chain and propose a Multi Hold&Fire algorithm that obtains the differences between both retinas.Ministerio de Ciencia e Innovación TEC2009-10639-C04-0